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So almost every single one of them. As necessary, delays were changed to be a function of a parameter that is based on the number of RAM wait states.
Doc - No change. Icarus Verilog version 0. This is now used to instantiate the semaphore registers. Testbench - Added capability to insert wait states on RAM access.
In the old design WISHBONE read cycles required the address to be decoded and the read data to be latched in the first cycle and the there was a whole cycle to drive the read data bus. The new design latches the address in the first cycle then decodes the address and outputs the data in the second cycle. The WISHBONE bus doesn't require the address or data to be latched for multi-cycle operation but by doing this it is hoped some power will be saved in the combinational logic by reducing the decoding activity at each address change.
Testbench - No change. Updates to testbench -- Extensive changes to testbench. The bus arbitration module has been completely rewritten. It now completely controls access to the system bus and RAM. The Xgate modules master and slave buses are fully integrated with the bus arbitration module and the system bus. The new testbench looks a lot more like a real system environment. Updates to User Guide -- Minor corrections to instruction set details. Needs more review on condition code settings.
There is a bug in DEBUG mode that is sensitive to number of preceding instructions and wait states that needs to be resolved. Updates to testbench -- Updates to User Guide -- First pass with instruction set details. Deleted two stack pointer registers. Updates to testbench -- Updates to User Guide -- Minor cleanup. Updates to testbench, Moved RAM.
Causes timing problems when master is polling Xgate registers durning debug mode tests. Will probably change RAM model to dual port in next revision. Updates to User Guide. Updates to testbench, added timeout and total error count. Updates to User Guide Created the sw directory and copied over the software stuff from the bench directory. Single Step Command in debug mode working. Software error interrupt added. And since it's fixed to reset only - you are pushed a bit to try to run your code in simulator or use full featured but costly emulator.
Too bad. Could it be some uninitialized pointer variable on stack? I use CW Standard edition, 4. How can it break on reset? Debugger could tell you it's illegal address reset by reading ILAF bit :- but can't tell you what caused it and were.
So I really see no reason why the RTC should go wrong? Looking at the ASM is indeed a good idea to make sure the compiler did its job properly.
You can also check in the Memory window of the debugger that the Software in the MCU memory matches what you programmed to rule out any flash cell worn out. Reset is immediate and 'resets' most registers but not all. As you know where the fault occurs, you can trigger the Debug module to trace the execution.
A reset does 'reset' the configuration of the Debug module, however it keeps the content of the trace to allow tracing through Reset. What memory model are you using and when you remove the piece of code, does it change the compilation of the code which fails. I like when things are weird. Regards, Alban. After I hit reset or do intentional illegal access reset - I see trace emptied. I don't see any option in multilink or in trigger settings that could help tracing through reset. Is CW 4. Thanks Edward.
However the buffer itself is not affected by a illegal address reset. May be you need to reconfigure the module as it was before the reset to access the trace.
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